1. Field of the Invention
The present invention relates to class AB amplifiers, and in particular, to low voltage class AB amplifiers with gain boosting and reduced power supply voltage requirements.
2. Description of the Related Art
As the demand for portable, battery operated devices has increased and transistor geometries continue to shrink, the use of low voltage circuits (i.e., circuits which operate at reduced power supply voltages, such as 2.5 and 1.8 volts) continue to increase. However, as the power supply voltage decreases, it becomes more difficult to maintain sufficiently high gain without increasing the complexity of the circuitry. For example, in low voltage circuits, high DC gain is generally achieved by cascading several gain stages. However, this can significantly increase the complexity of the circuit. This is particularly undesirable in the case of integrated circuits which have already become, and continue to be, increasingly complex already.
A more elegant solution is the use of gain boosting. Gain boosting is a technique by which an amplifier is used to enhance the output impedance of a gain stage and thereby increase the voltage gain when driving a high impedance load such as the gate terminal of a metal oxide semiconductor field effect transistor (MOSFET).
Referring to FIG. 1, one technique of gain boosting involves the use of an operational amplifier A to control the gate of a cascode transistor M used for amplifying an input current signal i.sub.in which has been generated by a preceding transconductance stage (not shown) which, in turn, has converted an input voltage to this input current i.sub.in. As is well known, in a traditional cascode circuit, the source terminal of the cascode transistor experiences a small voltage variation (due to the varying current flowing through the channel of the transistor and the finite source impedance) which modulates the input signal current i.sub.in. However, adding the amplifier A in this manner creates a feedback loop (due to the connection of the source terminal to the inverting input of the amplifier A) which fixes the voltage at the source terminal at the potential of the reference voltage V.sub.ref (applied at the non-inverting input of the amplifier A). This forces all of the input signal current i.sub.in to go into the cascode transistor M and the impedance at the source terminal of the cascode transistor M to be reduced. Since all of the current flowing into the source terminal of the cascode device will reappear at its drain terminal, the circuit now becomes an almost ideal current source, thereby providing a very high output impedance Z.sub.out. A small signal analysis of this circuit will indicate that the output impedance Z.sub.out is increased and the input impedance Z.sub.in is decreased as represented below in Equations 1 and 2 (where: g.sub.m =transconductance of transistor M; A=gain of amplifier A; r.sub.O1 =output resistance of transistor M; and r.sub.O2 =output resistance of current sink circuit I2). ##EQU1##
Referring to FIG. 2, one circuit design that makes use of gain boosting to achieve high DC gain amplifies a differential input current signal i.sub.in1 /i.sub.in2 to generate a single-ended output voltage V.sub.out. (Further discussion of this circuit can be found in Hogervorst et al., "A Programmable 3-V CMOS Rail-to-Rail Opamp With Gain Boosting For Driving Heavy Resistive Loads," IEEE International Symposium on Circuits and Systems Proceedings, Apr. 30-May 3, 1995, pp. 1544-47, which is incorporated herein by reference.) This circuit uses operational amplifiers A1 (transistors M51, M52 and M54) and A2 (transistors M55, M56 and M58) to provide gain boosting for cascode transistors M23 and M27 which amplify the two input signal components i.sub.in1, i.sub.in2. The resulting amplified signals drive the gate terminals of the class AB output transistors M65, M60.
In accordance with the foregoing discussion, the effective input impedances at the source terminals of the cascode transistors M23, M27 are reduced by the actions of the gain boosting circuits A1, A2, thereby allowing all of the signal currents i.sub.in1, i.sub.in2 to flow into the cascode transistors M23, M27. A major disadvantage of this feed forward type of circuit, however, is the fact that it has a relatively high minimum operating voltage requirement (V.sub.DD(min) -V.sub.SS) of approximately 2.7 volts. In terms of the NMOS transistors, this minimum operating voltage (V.sub.DD(min) -V.sub.SS) reflects the sum of two active transistor input bias potentials, i.e., the gate-source bias potentials of transistors M60 and M46, and an active transistor output bias potential, i.e., the saturated drain-source bias potential of the MOSFET providing the bias current I.sub.bias for transistors M44 and M45. In terms of the PMOS transistors, this minimum operating voltage (V.sub.DD(min) -V.sub.SS) reflects the gate-source voltages of transistors M65 and M42 and the saturated drain-source voltage of the PMOS transistor providing the bias current I.sub.bias for transistors M40 and M41. (As between the two, the minimum voltage requirement imposed by the PMOS transistors will be more stringent due to their higher threshold voltage.) Accordingly, this minimum voltage requirement makes this circuit unsuitable for operation with a 1.8 volt power supply voltage.
Referring to FIG. 3, another low voltage class AB amplifier design does provide for operation at a minimum operating voltage (V.sub.DD(min) -V.sub.SS) of approximately 1.8 volts. (Further discussion of this circuit can be found in De Langen et al., "Compact 1.8 V Low-Power CMOS Operational Amplifier Cells for VLSI," ISSCC Digest of Technical Papers, February 1997, pp. 346, 347 and 483, which is incorporated herein by reference.) In this circuit, two differential input current signals -i.sub.in1 /+i.sub.in1, -i.sub.in2 /+i.sub.in2, which are generated by a preceding transconductance stage (not shown), are amplified. The positive phase +i.sub.in1 of the first input current signal i.sub.in1 drives cascode transistors M15A and M15B, while the positive phase +i.sub.in2 of the second input current signal i.sub.in2 drives cascode transistors M13A and M13B. These four transistors M15A, M15B, M13A, M13B also form a differential amplifier for a class AB control. Transistors M60, M61, M62 and M63 form a low voltage class AB feedback current sensing circuit. When the output terminal (common node connection of the drain terminals of transistors M100 and M101) is sourcing or sinking an output current i.sub.o (i.e., pulling the output voltage v.sub.out up or down, respectively), these four transistors M60-M63 generate a feedback current I.sub.ABfb proportional to the current i.sub.100 (or i.sub.101) in the "idle" output device M100 (or M101) (I.sub.ABfb .varies. lesser of i.sub.100 and i.sub.101 ). When the output current i.sub.o is zero (i.sub.100 =i.sub.101), these transistors M60-M63 generate a feedback current I.sub.ABfb proportional to the quiescent current flowing in the output devices M100, M101 (I.sub.ABfb .varies. i.sub.100, i.sub.101). This feedback current I.sub.ABfb is delivered to a diode connected transistor M47 and is regulated by the class AB amplifier.
This circuit has a minimum operating voltage which is equal to the sum of one gate-source bias potential and two saturated drain-source bias potentials. In terms of the NMOS transistors, this would be the sum of the gate-source bias of transistor M101 and the drain-source bias potentials of transistor M15B and the current source used to generate the bias current I.sub.bias. In terms of the PMOS transistors, the relevant bias potentials are for transistors M100, M13A and M13. As noted above, this circuit is suitable for operation at 1.8 volts power supply voltage. However, a significant disadvantage of this feedback type of circuit is the limited DC gain due to the limited number (two) of gain stages.